1. Field of the Invention
The present invention is related to the field of data communications, and more specifically towards systems, circuits and methods for adapting taps of a decision feedback equalizer in a receiver.
2. Art Background
Electronic circuits utilize serial data transmission to transmit data among one or more circuits. In general, serial data transmission involves transmitting bits in a single bit stream at a predetermined data rate. The data rate is expressed as the number of bits transmitted per second (“bps”). Typically, to transfer data between circuits, the sending circuit employs a transmitter that modulates and sends data using a local clock. The local clock provides the timing for the bit rate. The receiving circuit employs a receiver to recover the data, and in some cases, the clock. The receiver circuit recovers the serial bit stream of data by sampling the bit stream at the specified data rate.
Techniques have been developed in an attempt to optimize the performance of a receiver in order to improve the bit error rate of the data. For example, current receiver optimization techniques involve changing the gain of a variable gain amplifier to reduce the bit error rate of data. Another current example involves adjusting a clock signal in order to optimize the data decision point in the time domain. However, these techniques do not provide the flexibility in the optimization of other components within the receiver.
Accordingly, it is highly desirable to develop a receiver with components where the parameters of the components can be flexibly adapted in response to the bit error rate of the data so that the receiver is optimized.